Verilog Code for Signal/Square wave Generator
Signal/Square wave Generator:
In this code, We implemented a Square wave generator. For this, firstly clock frequency is initialized and after then the counter is defined for the toggling of clock. Now, in the always block, at the positive edge of clock, if (!reset), then counter=0; and square_wave_reg=0 , else if counter=0; then square wave will toggle(i.e it behaves as invert of original square wave) and the counter = (clock freq/2-1) or else counter gets decremented by 1. Hence, our square wave is generated.
Verilog Code for Signal/Square wave Generator:
module signal_generator(input clk,
input rst,
output sq_wave
);
localparam CLOCK_FREQUENCY = 100000000;
// Counter for toggling of clock
integer counter = 0;
reg sq_wave_reg = 0;
assign sq_wave = sq_wave_reg;
always @(posedge clk)
begin
if (!rst)
begin
counter <= 8'h00;
sq_wave_reg <= 1'b0;
end
else begin
// If counter is zero, toggle
sq_wave_reg if (counter == 8'h00)
begin
sq_wave_reg <= ~sq_wave_reg;
// Generate 1Hz Frequency
counter <= CLOCK_FREQUENCY/2 - 1;
end
// Else count down
else
counter <= counter - 1;
end
end
endmodule
OUTPUT:
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