Verilog Code for 3 bit Counter
3 Bit Counter:
Digital counters count upwards from zero to some predetermined count value on the application of a clock signal. Once the count value is reached, resetting them returns the counter back to zero to start again. At the positive edge of clock if reset=1; count=0; and if enable=1; count gets incremented by 1 always.
In 3 bit counter,we can count 000 to 111 in binary form.After its higher value it will start counting counting from 000.
Verilog Code for 3 bit Counter:
module counter(count,clk,reset,enable);
input clk,enable,reset;
wire clk,enable,reset;
output count;
reg[2:0] count;
initial count=3'b0;
always@(reset)
begin
if(reset==1)
begin count<=0;
end
end
always@(posedge clk)
begin
if(enable==1)
begin
count<=count+1;
end
end
endmodule
OUTPUT:
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