Serial Adder using FSM:
We have to design FSM, so we implemented serial adder using FSM. Serial adder takes 3 input and gives 2 output as sum and carry.
Top module is defined, we define the state assignments, here we assign s0=0, and s1=1. A register present is also defined. Now, always block is defined for reset that is, always at the positive edge of clock, when reset =1, present =s0, else present takes the value of cout. Now 2nd always block is defined, case block is defined which takes the value of present:
➢ Begin the s0 loop, sum = a x-or b. If input is a&b, then cout=s1, else it takes the value of present. ➢ Begin the s1 loop, sum = a x-nor b. If input is not of a&b, then cout=s0; else it takes the value of present.
➢ The default value is taken as s0 always, case is ended and loop is also ends. In this way, serial adder using FSM is implemented.
Verilog Code for Serial Adder using FSM:
module serial_adder_fsm(a,b,cin ,clk,reset,sum,cout);
output reg sum,cout;
input a,b,cin,clk,reset;
reg present;
//state assignment
parameter s0=1'b0;
parameter s1=1'b1;
//reset facility
always@(posedge clk)
begin
if(reset)
present<=s0;
else
present<=cout;
end
initial
begin
present=cin;
end
always@(posedge clk)
begin
case(present)
s0: begin
sum=a^b;
if(a&b)
cout=s1;
else
cout=present;
end
s1: begin
sum= ~(a^b);
if (~a&~b)
cout=s0;
else
cout=present;
end
default:cout=s0;
endcase
end
endmodule
OUTPUT:
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