Verilog Code for SR Latch

Verilog Code for SR Latch

SR Latch:

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated.

Verilog Code for SR Latch:

SR Latch using NAND gate

module sr_latch(q,qbar,Sbar,Rbar);

output q,qbar;

input Sbar,Rbar;

nand n1(q,Sbar,qbar);

nand n2(qbar,Rbar,q);

endmodule

OUTPUT: