Verilog Code for duty cycle

Verilog Code for duty cycle
40% duty cycle:

We have to generate a clock of 40% duty cycle, so we take an input enable and an output clock. Since it is a sequential circuit, therefore output is taken as reg(register).  Now always block is defined with the enable condition, i.e: if enable==1; clock==0; else it would stop the execution, that’s why $finish is used. Also, after 6 and 10 cycles of clock, it will invert itself, so that we get clock of 40% duty cycle.  Hence clock is generated.

Verilog Code for Clock having 40% duty cycle:

module clock (enable, clock) ;
input enable;
output clock;
reg clock; 
always@(enable) 
begin if (enable==1'b1)  
begin clock = 1'b0;
end 
else 
$finish; 
end  
always 
begin 
#6 clock <=~clock; 
#10clock<=~clock; 
end 
endmodule




Output:








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