Verilog Code for Frequency/Clock Divider
Frequency/Clock Divider by 2:
We have to generate a frequency divider, which divides the clock half of its cycle. So we take two variables a and b. a as input and b as output, output is declared as reg because of sequential circuit. Now always block is defined, that is always at the negative edge of clock If b==a; Then b=~ a( b takes the invert value of a) Or else takes the same value as a, hence the frequency divider is generated.
Verilog code for Frequency/Clock divider by factor of 2:
module frequencydivider(a,b);
input a;
output b;
reg b=1'b1;
always@(negedge a)
begin
if(b==a)
b=~a;
else
b=a;
end
endmodule
Output:
0 Comments