Verilog Code for Shifter Unit

Shifter Unit:

Shifter unit shifts the most significant bits either to the left or to the right. In this code, two inputs are taken, 1st =8bit and 2nd=3bit. Always block is defined for these inputs such that if(s[2]=0), then left shift occurs if it is 1, then right shift occurs. Three cases are taken considering the s[0] and s[1] bits and accordingly bits are shifted.

Verilog Code for Shifter Unit:

module shifter_unit(input [7:0]a,

                               input [2:0]s,

                               output[7:0] out

                          ); 

reg[7:0]out; 

always@(a or s) 

if(s[2]===1'b0) 

begin:left_shift 

case({s[1],s[0]})  

2'b00:begin:by_unit_1        

out <= a<<1;  

end  

2'b01:begin:by_unit_2        

out <= a<<2;  

end  

2'b10:begin:by_unit_3         

out <= a<<3;   

end  

default:out <= a; 

endcase 

end

else if(s[2]===1'b1)    

begin:right_shift 

case({s[1],s[0]})  

2'b00:begin:by_unit_1        

out <= a>>1;  

end  

2'b01:begin:by_unit_2        

out <= a>>2;  

end  

2'b10:begin:by_unit_3         

out <= a>>3;   

end  

default: out<=a; 

endcase 

end 

endmodule 

OUTPUT: