Left/Right Shifter
Left shifter: When shifting left with a logical shift left, the most-significant bit is lost and 0 bit is inserted on the other hand.
Right shifter: When shifting right with a logical right shift, the least-significant bit is lost and 0 bit is inserted on the other hand.
By the left/right shifter we can perform both the operation from single code with only changing in one input.
Verilog Code for Left/Right shifter:
`define left_shift 2'b00
`define right_shift 2'b01
`define aleft_shift 2'b10
`define aright_shift 2'b11
module shift_unit(ans,select,n,clk);
output reg [3:0]ans;
input[1:0] select;
input clk;
input[3:0] n;
always@(negedge clk)
begin
case(select)
`left_shift:begin ans = n<<1;
end
`right_shift:begin ans= n>>1;
//n=ans;
end
`aleft_shift:begin ans=n<<<1;
//n=ans;
end
`aright_shift:begin ans=n>>>1;
//n=ans;
end
endcase
end
always@(posedge clk)
begin
case(select)
`left_shift:begin ans = ans<<1;
end
`right_shift:begin ans= ans>>1;
end
`aleft_shift:begin ans=ans<<<1;
end
`aright_shift:begin ans=ans>>>1;
end
endcase
end
endmodule
Output:
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