Verilog Code for Clock Divided by 3
Clock Divided by 3:
We have to generate a clock divided by 3. So we take variables like input clock(clk_in) , reset and output as clk_out. We also used two internal variables pos_cnt and neg_cnt.
pos_cnt and neg_cnt are positive and negative counters , which count the posedge and negedge of input clock.They will perform their operation and assign the output clock.
Verilog Code for Clock Divided by 3:
module clock_divider_by_3(clk_in,reset,clk_out);
input clk_in;//input clock
input reset;//reset input
output clk_out;//output clock
//internal variables
reg[1:0]pos_cnt=0;
reg[1:0]neg_cnt=0;
//posedge counter
always@(posedge clk_in)
begin
if(reset)
pos_cnt<=0;
else
pos_cnt<=(pos_cnt==2)?0:pos_cnt+1;
end
//negedge counter
always@(negedge clk_in)
begin
if(reset)
neg_cnt<=0;
else
neg_cnt<=(neg_cnt==2)?0:neg_cnt+1;
end
assign clk_out=((pos_cnt!=2)&&(neg_cnt!=2));
endmodule
OUTPUT:
0 Comments