Verilog Code for ALU
ALU:
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit (CPU) of a computer.
ALU contains the logical circuit to perform mathematical operations like subtraction,addition, multiplication, division, logical operations and logical shifts on the values.In this logic case block is defined, the output produces the value according to our case.
Verilog Code for ALU:
module alu(a,b,c,y);
input [2:0]c;
input [2:0]a,b;
output reg[7:0]y;
always@(a,b,c)
begin
case(c)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=a&b;
3'b011:y=a|b;
3'b100:y=a^b;
3'b101:y=a+1;
3'b110:y=a-1;
3'b111: begin y=a;
y=y>>1'b1 ;
end
endcase
$display("output=%b",y);
end
endmodule
OUTPUT:
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