Verilog code for 4X1 MUX using Dataflow

4X1 MUX

A multiplexer or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through the output. It is act as a remote, we have several input into our television but by the help of remote we only select one of them. In the multiplexer we have select lines for selecting the appropriate output from several inputs.


              This multiplexer has 4 inputs, 1 output, and 2 control signals/select lines. Each binary combination of control signal will select one out of four input. Output is produced when it satisfy the assign condition.


Verilog code for 4X1 MUX :

module mux_4x1_dataflow(out,i0,i1,i2,i3,s0,s1); output out;
input i0,i1,i2,i3,s0,s1;
assign out=(~s1&~s0&i0)|(~s1&s0&i1)|(s1&~s0&i2)|(s1&s0&i3);
endmodule

Output:


  

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