Verilog Code for T flip flop using udp

T flip flop using udp:

We know that T flipflop produces the output as the toggle of input. Since, it is a sequential UDP, output is taken as reg. State table is declared and the module is defined in which UDP of T flipflop is instantiated. Output is observed in the waveform. Hence, T flipflop is implemented.

Verilog Code for T flip flop using udp:

//define edge sensitive sequential udp. 

primitive tff_udp(regq,t,clk); 

output regq ; 

input t,clk; 

table 

//  t  clk : q; 

    0    1 : 1; 

    1    0 : 0; 

endtable 

endprimitive  

//terminal declarations 

module UDP_TFF(regq,t,clk); 

output regq; 

input  t,clk; 

tff_udp u1(regq,t,clk); 

endmodule

OUTPUT: