Verilog Code for D flipflop using udp

D flipflop using udp:

D flipflop produces the same output as input. Since, it is a sequential UDP, output is taken as reg. State table is declared and the module is defined in which UDP of D flipflop is instantiated. Output is observed in the waveform. Hence, d flip flop using UDP is implemented.

Verilog Code for D flipflop using udp:

//define edge sensitive sequential udp. 

primitive dflipflop_udp(regq,d,clk); 

output regq ; 

input d,clk;  

table 

//d  clk : q; 

  0    1  : 0; 

  1    0  : 1; 

endtable 

endprimitive  

//terminal declarations 

module UDP_DFF(regq,d,clk); 

output regq; 

input  d,clk; 

dflipflop_udp u1(regq,d,clk); 

endmodule   

OUTPUT: