Verilog Code for Swapping

Swapping:

Swapping means interchanging. We have defined input as clock and two output as reg a and b.

Initial value of a=0; and b=1; 

Now, at the positive edge of clock, a gets the value of b and b gets the value of a. also, non-blocking statements are used to avoid race condition.

Verilog Code for Swapping:

module swapping(a,b,clk); 

input clk; 

output reg a,b; 

initial 

begin 

a=1'b0; 

b=1'b1; 

end

always@(posedge clk) 

begin 

a<=b; 

b<=a; 

end 

endmodule 

OUTPUT: