Verilog Code for Parity Encoder

Parity Encoder:

Parity Encoder is a combinational circuit,which is used to find the even and odd parity from the binary sequence.

In this code,the data flow statements are used for genrate a Parity Encoder.

Verilog Code for Parity Encoder:

module parity_gen(ep,op,x); 

output ep,op; 

input [8:0]x; 

assign ep=^x; 

assign op=~ep; 

endmodule

OUTPUT: