Verilog code for D Latch

D Latch:

Latch is level sensitive and asynchronous. Clock and D are taken as input and Q(1st state), out(next state) as outputs. D latch is implemented using NAND gate.  
Its output depends on clock, that is: 
➢ When clock is high, Q produces the output same as input and the next state produces the output as the invert of input.  
➢ When clock is low, it produces the output (both present and next state) as latch.


Verilog Code for D Latch:

module d_latch(Q,out,clk,d); 
output Q,out; 
input clk,d; 
wire a,b; 
nand n1(a,clk,d); 
nand n2(b,clk,a); 
nand n3(Q,a,out); 
nand n4(out,b,Q); 
endmodule

OUTPUT:


Post a Comment

0 Comments