Serial Parity:
When an input comes, the even parity generator checks whether the total number of 1’s received till then are even or odd. If even then the output becomes “0” [Out = 0], otherwise output would be “1” [Out = 1].
S0: Even number of 1’s received
for input “0”: Since the present state represents that till now even number of 1’s are received, an input “0” will keep the number of 1’s received as even. So, the next state would be S0 and the output (parity bit generated) would be “0”.
for input “1”: An input “1” will make the number of 1’s received as odd. So, the next state would be S1 and the output (parity bit generated) would be "1" .
S1: Odd number of 1’s received
for input “0”: Since the present state represents that till now odd number of 1’s are received, an input “0” will keep the number of 1’s received as odd. So, the next state would be S1 and the output (parity bit generated) would be “1”.
for input “1”: An input “1” will make the number of 1’s received as even. So, the next state would be S0 and the output (parity bit generated) would be “0”.
Verilog Code for Serial Parity:
module serial_parityfsm(ep,op,x,clk,reset);
output reg ep,op;
input x;
input clk,reset;
reg present,next;
parameter s0=1'b0;
parameter s1=1'b1;
always@(posedge clk)
begin if(reset)
present<=s0;
else
present<=next;
end
always@(x)
begin
case(present)
s0: if (x==0)
begin
next=present;
ep=0;
$display("ep=%b",ep);
end
else
begin
next=s1;
ep=1;
$display("ep=%b",ep);
end
s1: if (x==0)
begin
next=present;
op=1;
$display("op=%b",op);
else
begin
next=s0;
ep=0;
$display("op=%b",op);
end
default: next=s0;
endcase
end
endmodule
OUTPUT:
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