Verilog Code for Parameterized Multiplier using Generate Condition

Parameterized Multiplier using Generate Condition:

A Binary Multiplier is a digital circuit used in digital electronics to multiply two binary numbers and provide the result as output. The method used to multiply two binary numbers is similar to the method taught to school children for multiplying decimal numbers which is based on calculating partial product, shifting them and adding them together. Similar approach is used to multiply two binary numbers. Long multiplicand is multiplied by 0 or 1 which is much easier than decimal multiplication as product by 0 or 1 is 0 or same number respectively.
When we want to the same code become for any other number then Parameterized codes are used.For example if we write a code for 2 numbers and we want to the same code become for 5 numbers,then parameter is used.
Generate Conditions are used in loops and Generate conditions generate "genvar".

Verilog Code for Parameterized Multiplier using Generate Condition:

module parametrized_multiplier(   

                                                input [N-1:0] a, b,   

                                               output [2*N-1:0] y   

                                                    ); 

parameter N = 8; 

wire [N*N-1:0] p;  

genvar i; 

assign p[N-1 : 0] = a[0] ? b : 0; 

generate for (i = 1; i < N; i = i+1) begin:gen     

assign p[N*(i+1)-1 : N*i] = (a[i] ? b << i : 0) +  p[N*i-1 : N*(i-1)]; 

end 

endgenerate  

assign y = p[N*N-1 : N*(N-1)];  

endmodule 

OUTPUT: