Verilog Code for Asymmetric Sequence Generator(task)

Asymmetric Sequence Generator(task):

As task can directly operate on reg variables defined in the module. Here, operation is directly performed on the reg variable clock to continuously produce an asymmetric sequence. The clock is initialized with an initialization sequence.

Verilog Code for Asymmetric Sequence Generator(task):

module sequence; 

reg clk; 

initial init_sequence; 

always  

begin  

asymmetric_sequence;//invoke the task 

symmetric sequence 

end 

//initilization sequence  

task init_sequence; 

begin   

clk=1'b0; 

end 

endtask  

//define task to generate asymmetric seq 

//operate dir on the clock  

task asymmetric_sequence; 

begin  

#12clk=1'b0;  

#5clk=1'b0;  

#3clk=1'b0;  

#10clk=1'b1; 

end 

endtask 

endmodule 

OUTPUT: