32 bit Adder:
A 32-bit adder is implemented using generate case block. We are using genvar(used to declare variables used only in the evaluation of generate block). The value of genvar can be defined only by a generate loop. Here genvar i and j are used, generate block is used in which a condition is generated using for loop.
Verilog Code for 32 bit Adder:
module adder_32bit(a,b,cin,sum,cout);
parameter
N=32;//we can use any value using parameter.
input [N-1:0]a;//n
bit input a.
input [N-1:0]b;//n
bit input b.
input cin; //carry input.
inout
[N:1]cout;
output [N-1:0]sum;
wire
[N-1:0]w1,w2,w3;
//sum for first
bit.
xor
x1(sum[0],a[0],b[0],cin);
//loop for sum.
genvar i;//it is
used for loop'
generate
for(i=1;i<N;i=i+1) begin : sum_loop
xor
x2(sum[i],a[i],b[i],cout[i]);
end
endgenerate
//carry out for
first bit.
and
a1(w1[0],a[0],b[0]);
and a2(w2[0],b[0],cin);
and
a3(w3[0],a[0],cin);
or
o1(cout[1],w1[0],w2[0],w3[0]);
//loop for carry
out.
genvar j;//it is
used for loop.
generate
for(j=1;j<N;j=j+1) begin : carry_loop
and
a1(w1[j],a[j],b[j]);
and
a2(w2[j],b[j],cout[j]);
and
a3(w3[j],a[j],cout[j]);
or o1(cout[j+1],w1[j],w2[j],w3[j]);
end
endgenerate
endmodule
OUTPUT:
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