Verilog Code for Synchronous Counter with Reset
4 bit Synchronous Counter with Reset:
Digital counters count upwards from zero to some pre-determined count value on the application of a clock signal. Once the count value is reached, resetting them returns the counter back to zero to start again.
Clock and reset are given as input and count is taken as output. When reset=1, count gets the value 0 and the loop is ended. Now, another always block is defined which gets the value according to the positive edge of clock i.e always at the positive edge of clock count gets incremented by one and the loop ends.
Verilog Code for 4 bit Synchronous Counter with Reset:
module fourbit_syn_counter(count,clk,reset);
input clk,reset;
wire clk,reset;
output count;
reg[3:0] count;
initial count=4'b0;
always@(reset)
begin
if(reset==1)
begin count<=0;
end //end of if
end
always@(posedge clk)
begin
count<=count+1;
end
endmodule
OUTPUT:
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