4X1 MUX using UDP
A multiplexer or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through the output.
User Defined Primitives can describe both combinational and sequential circuits. The behavioral description is provided as a truth table.
The UDP declaration starts with the keyword primitive and ends with the keyword endprimitive. A port list, an output port declaration and input ports declaration are similar to their equivalents in a module declaration.
Verilog code for 4X1 MUX using UDP:
primitive mux_udp(out,s0,s1,i0,i1,i2,i3);
output out;
input s0,s1;
input i0,i1,i2,i3;
table
//s0 s1 i0 i1 i2 i3 : out;
0 0 0 ? ? ? : 0;
0 0 1 ? ? ? : 1;
0 1 ? 0 ? ? : 0;
0 1 ? 1 ? ? : 1;
1 0 ? ? 0 ? : 0;
1 0 ? ? 1 ? : 1;
1 1 ? ? ? 0 : 0;
1 1 ? ? ? 1 : 1;
endtable
endprimitive
module UDP_MUX(out,s0,s1,i0,i1,i2,i3); output out;
input s0,s1; input i0,i1,i2,i3;
mux_udp u1(out,s0,s1,i0,i1,i2,i3);
endmodule
Output:
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